1.Field of the Invention
The present invention relates to a CMOS D-type flip-flop that can be loaded asynchronously to a clock input.
2. Discussion of the Prior Art
A flip-flop is a logic circuit that includes feedback so that its output state is a function not only of the input, but also of the previous history of the input. Thus, a flip-flop may be used as a memory element.
For example, a flip-flop has two outputs, usually called Q and Q' to indicate that if the Q output is a 1, then the Q' output must be a 0. A momentary input signal will cause the outputs to "flip" so that the Q output becomes a 0 and the Q' output becomes a 1. The two output signals will remain in these states even though the input signal is removed.
An edge-triggered D-type flip-flop transfers a data input D to the Q and Q' outputs on the transitions of a clock CK. However, there are circumstances in which it is necessary to load data into the flip-flop at times other than at the clock transitions, i.e. asynchronously to the clock. For example, if the flip-flop is to be used as a timer or a counter, then an initial value must be loaded to begin the timing or the count. Also, asynchronous events may occur that require that the data value currently stored in the flip-flop be overridden.
An asynchronously loadable D-type flip-flop can be obtained by utilizing a conventional D flip-flop with asynchronous clear and preset, such as a generic HC74 device, and providing external logic to clear or preset when loading a 0 or 1, respectively. A conventional flip-flop of this type is illustrated in FIG. 1. While this approach works well, additional logic is required to steer the preset and clear lines to perform the load function.